1. Field of the Invention
The present invention relates to hermetically sealed semiconductor chips. More particularly, the present invention relates to coating at least the active surface of a flip chip with a silicon nitride sealing layer.
2. State of the Art
Chip On Board ("COB") techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding ("TAB"). A flip chip is a semiconductor chip or die that has a pattern or array of spaced terminals or pads on its active surface for face down mounting of the chip to a printed circuit board or other conductor-carrying substrate. Generally, the flip chip active surface carries one of the following types of electrical connector elements: Ball Grid Array ("BGA")--wherein an array of minute solder balls (sometimes called C4 connections, for controlled-collapse-chip-connect) or other conductive material disposed on the surface of a flip chip that attaches to the substrate trace terminals or connecting pads ("the attachment surface"); or a Slightly Larger than Integrated Circuit Carrier ("SLICC")--which is similar to a BGA, but having a smaller solder ball/conductive material pitch and diameter than a BGA. With the BGA or SLICC, the solder or other conductive ball or element arrangement on the flip chip must be a mirror-image of the connecting pads on the printed circuit board so that precise connection is made. When solder balls are employed, the flip chip is bonded (electrically and mechanically connected) to the printed circuit board by reflowing the solder balls. Other conductive elements such as conductive epoxies or conductor-filled epoxies or other polymers may be employed in lieu of solder balls and heat-cured after chip attachment.
Semiconductor chips must be able to withstand a wide variety of environmental conditions such as moisture, ion bombardment, heat and abrasion. A significant amount of work has been directed toward various protective measures to minimize the exposure of semiconductor chips to these environmental conditions in order to increase their reliability and operating life.
Many prior art processes for protecting semiconductor chips have involved sealing or encapsulating the chips after they have been attached to their respective lead frame, printed circuit board, or other carrier substrate. Plastic encapsulation of semiconductor chip is currently the most common form of packaging chips. Plastic encapsulation normally consists of encasing a leadframe-mounted semiconductor die in plastic under pressure in a transfer molding process. Furthermore, so-called "glob top" (commonly silicones and epoxies) and underfill (commonly epoxies) materials have been used to protect chips secured on a printed circuit board (such as an FR-4 glass-epoxy board), or ceramic or silicon substrate. A non-conductive polymer underfill is generally disposed between the active surface of a "flipped" semiconductor chip and the printed circuit board or other carrier substrate for environmental protection and to enhance the mechanical attachment of the semiconductor die to the substrate. An overfill encapsulant of viscous liquid or gelled silicone or epoxy (glob top) is sometimes applied over an entire assembly after COB attachment. In short, it is known in the art to use layers of silicones, polyimides, epoxies, plastics, and the like for protection of the COB assemblies.
While transfer-molded plastic encapsulation and glob tops are effective methods of protecting the semiconductor die from abrasion and some mechanical damage, such approaches are of limited value, since most such packaging structures are permeable to environmental moisture and ions to a measurable degree. This permeability, however slight, leaves the semiconductor chip susceptible to degradation from electrochemical reactions with atmospheric contaminants. The numerous and extensive polymer/metal interfaces at the lead entries of an encapsulated semiconductor package afford ample opportunities for moisture ingress as well as allowing soluble ions present to provide an electrolyte for a corrosive failure mechanism of the semiconductor chip. Also, the extensive use of precious metals coupled with base metals in chips and packages provide DC galvanic potentials for electrochemical corrosion reactions and dendrite growth, which affect the performance and life of the encapsulated semiconductor chip.
As a result of the problems associated with the plastic encapsulation of semiconductor chips, it has been established as desirable to hermetically package chips to prevent external moisture and chemicals from contacting the semiconductor chip. U.S. Pat. No. 5,136,364 issued Aug. 4, 1992 to Byrne relates to hermetically sealing semiconductor chip bond pads to prevent moisture contamination along the interface of the multiple metal layers of typical bond pads. The hermetic sealing comprises layers of passivation materials wherein the upper passivation layer is a silicon dioxide and nitride combination or silicon carbide. The hermetic sealing can also include layers of glass and/or polyimide.
It is known to seal semiconductor chip active surface circuitry at the wafer stage of production by applying a passivation coating to the wafer with ceramic materials such as silica and/or silicon nitride by chemical vapor deposition ("CVD") techniques. See, for example, U.S. Pat. Nos. 5,046,161, 5,084,752 and 5,406,122. However, the subsequent etching back of the passivation coating at the bond pads of the semiconductor chip may damage the passivation coating adjacent the bond pads, thereby affecting the reliability of the chip and shortening the life of the chip due to environmental corrosion. The sides of the passivation etched from the bond pad edges can also be permeable.
In an attempt to hermetically seal semiconductor chips without the use of external packages, U.S. Pat. No. 5,481,135 issued Jan. 2, 1996 to Chandra et al. suggests the use of lightweight ceramic protective coatings, such as those derived from hydrogen silsesquizane and silicate esters. These coatings are applied to the active surface of a semiconductor chip at a wafer level. Although the bond pads are subsequently exposed by removing a portion of the ceramic protective coating, the resultant circuits are purported to remain hermetically sealed. However, the process of this patent requires the application of a diffusion barrier metal layer to protect the bond pads during the etching to expose the bond pads. A room temperature plasma deposition system capable of applying a low-stress silicon nitride over components on a circuit assembly is disclosed by L. Gates in "Sealed Chip-on-Board," Electronic Packaging & Production, September 1994, pp. 48-50 (the "Gates article"). In the described deposition process, a semiconductor die which is wire bonded to a substrate is subsequently entirely coated with silicon nitride. Thus, the silicon nitride covers the bond pads, bond wires, and other components of the assembly.
The disclosures of hermetically sealed semiconductor chips described above, with the exception of the Gates article, fail to provide a process for sealing a wafer or semiconductor chip without damage to the semiconductor chip or bond pads from back etching to expose the bond pads, unless additional processing steps are employed. Gates, moreover, does not address the complexities of hermetically sealing a flip chip type semiconductor die assembly. Therefore, it would be advantageous to develop a technique for simply, quickly and inexpensively forming a hermetic seal on in combination with commercially-available, widely-practiced semiconductor device fabrication techniques compatible with flip chip attachment.